IBM, AMD speed chips
p2pnet.net News:- AMD and IBM say they’ve developed a unique technology that results in up to a 24% transistor speed increase at the same power levels as similar transistors made without it.
And, they say, it works without the introduction of costly new production techniques, allowing for rapid integration into volume manufacturing using standard tools and materials.
“Faster, more power-efficient transistors are the building blocks of higher performance, lower power processors,” they say in a statement. “As transistors get smaller, they operate faster, but also risk operating at higher power and heat levels due to electrical leakage or inefficient switching.
“AMD and IBM’s jointly developed strained silicon helps overcome these challenges. In addition, this process makes AMD and IBM the first companies to introduce strained silicon that works with silicon-on-insulator (SOI) technology, resulting in an additive performance and power savings benefit.”
AMD says it will gradually integrate the new strained silicon technology into all of its 90nm processor platforms, including its future multi-core AMD64 processors with the first 90nm AMD64 processors using the technology slated to go out in the first half of 2005.
For its part, IBM plans to introduce the technology on multiple 90nm processor platforms, including its Power Architecture-based chips, with the first products scheduled to begin shipping in the same time frame.
The new strained silicon process, called "Dual Stress Liner," enhances the performance of both types of semiconductor transistors, called n-channel and p-channel transistors, by stretching silicon atoms in one transistor and compressing them in the other, say the companies.
The Dual Stress Liner with SOI technology was developed by engineers from IBM, AMD, Sony and Toshiba at IBM’s Semiconductor Research and Development Center (SRDC) in East Fishkill, NY, as well as engineers from AMD at its Fab 30 facility in Dresden, Germany, say the firms IBM and AMD.
December 13th, 2004 at 4:45 pm
AMD kicking some tail again.
December 14th, 2004 at 7:03 pm
I’m a little sceptical of the physics behind this (which is mentioned elsewhere).
I think molecular bonds can be stretched but atoms can not be stretched (at leadst for any perceptable length of time).
That is to say the separation between the silicon atoms can be stretched but
the atoms themselves are not stretched in anyway. I would think that any chips based on stretched material would be far more likely to breakdown under voltage due to the stressed nature of the material.
It’s time for the chip industry to move away from silicon.
December 15th, 2004 at 11:41 pm
Silicon is good because silicon is cheap and available. Other materials are hard to be forced at 90-nm, some of them are hard to be made with 1um litography scales.
The stretching is in fact just a 1 or 2% increase in the grid spacing. the atoms are just crystallized differently (I heard that AMD used grid-on-grid type stretching). Reliability stays the same. In other words: it is a more controlled basic SOI layer deposition process, that became comercially available. I also heard rumors that only one isotope of silicon has to be used for this process. Or is it one isotope (lighter) over another isotope (heavier)? That would make sense. The purity of the silicon is today almost absolute, so mass using only one isotope is only a small step.