IBM claims chip breakthrough
p2p news / p2pnet: In 1965 Intel co-founder Gordon Moore predicted the number of transistors on a single chip would double every year, later revising his estimate to say that would happen every two years.
Obviously, Moore’s Law, as this has come to be known, means sooner or later, a limit will be reached
But IBM says its discovery of how to change the way printed circuits are ‘printed’ on chips could both buy additional time and postpone “risky’ alternatives, and save the industry millions of dollars.
“IBM scientists have created the smallest, high-quality line patterns ever made using deep-ultraviolet (DUV, 193-nanometer) optical lithography – a technology currently used to essentially ‘print’ circuits on chips,” it says.
“The distinct and uniformly spaced ridges are only 29.9 nanometers wide (a nanometer is a billionth of a meter). This is less than one-third the size of the 90-nanometer features now in mass production and below the 32 nanometers that industry consensus held as the limit for optical lithography techniques.”
The company says the semiconductor industry has, “relied on continually shrinking circuits to drive increases in the performance and function of chips and the products that use them.”
But as fundamental scale limits of individual atoms and molecules are reached, IBM’s new result indicates that a “high-index immersion” variant of DUV lithography may be the answer, it says.
“Our goal is to push optical lithography as far as we can so the industry does not have to move to any expensive alternatives until absolutely necessary,” says Dr Robert D. Allen, manager of lithography materials at IBM’s Almaden Research Center. “This result is the strongest evidence to date that the industry may have at least seven years of breathing room before any radical changes in chip-making techniques would be needed.”
The pattern of well-defined and equally spaced 29.9-nanometer lines and spaces was created on a lithography test apparatus designed and built at IBM Almaden, using new materials developed by its collaborator, JSR Micro (Sunnyvale, California).
The first technical details will be presented today at the SPIE Microlithography 2006 conference being held in San Jose, California.
Also See:
IBM – IBM Research Demonstrates Path for Extending Current Chip-Making Technique, February 20, 2006
